Conventional semiconductor devices or integrated circuits (ICs) generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric layers and conductive paths or interconnects made of conductive materials. IC interconnects are usually formed by filling a conductive material such as copper into features (openings) formed in the dielectric layers. Such features include, but are not limited to, vias, cavities, and trenches that are filled to define lines, pads and contacts. In a typical integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias filled with contacts.
Recently, work has been carried out to develop high-density, low-capacitance vertical interconnect technologies for integrated circuit systems. These wafer level integration and packaging technologies are aimed at increasing IC system performance in terms of speed and reduced power consumption while reducing weight and volume. The vertical interconnects enable three dimensional (3-D) homogeneous integration of multiple layers of ICs as well as 3-D heterogeneous integration of multiple layers of ICs with various devices fabricated in different materials. Thus, 3-D integration includes integrating multiple ICs either at the chip or wafer level. The resulting multi-layer structures offer optimal short interconnect paths and large inter-layer signal bandwidth compared to the existing wire bonding technologies with high inductance, low speed, low wiring density and high cross talk.
3-D interconnect structures comprise larger features in terms of depths and widths, compared to the standard IC interconnect structures. Standard IC interconnect structures include sub-micron width vias and trenches at lower metal layers and may also have 50-100 micrometers (μm) wide lines and bond-pads, especially at the highest metal layers. Feature depth may range from 0.15-0.6 μm for lower metal levels and it may be in the range of 1-5 μm at the higher metal levels of typical IC interconnects. The aspect ratio (depth-to-width ratio) of small or narrow features in an IC interconnect is typically 2 or higher, whereas the aspect ratio of the larger features (e.g., wider than about 3 μm in the above example) are smaller than 1, typically smaller than 0.1 for lower metal layers such as M1 and M2, the lowest two levels of metal in an integrated circuit. In comparison, 3-D integration structures are much deeper. Although their widths are large, their aspect ratios are also larger than 1. In other words, the features have depths larger than their widths. These structures typically include vias with diameters or widths of 10-100 μm and aspect ratios of more than 5, even higher than 10. Therefore, processes applicable to filling the narrow features of IC interconnects with a metal do not necessarily apply to filling the wider and deeper, i.e., larger, features of 3-D interconnects.
The most commonly used processing approach for filling a conductor into IC interconnect damascene vias or trenches is electrochemical deposition or electroplating. Electroplating techniques are relatively low cost. In addition, they have the capability of filling narrow and high aspect ratio features in a bottom-up fashion so that voids and other defects do not form in the features. In an electroplating process, a conductive material such as copper is deposited to fill such features. The material is then annealed for grain growth. Then, a material removal technique, such as chemical mechanical polishing (CMP), is employed to planarize and remove the excess metal or overburden from the top surface of the wafer, leaving conductive material only in the features. It should be noted that for IC interconnect formation it is beneficial to deposit some overburden thickness onto the top surface or field regions of the wafer surface. Such overburden helps grain growth within the small features and helps reduce resistance of copper within the features.
3-D integration using the IC interconnect approaches described above are challenging. First of all, deposition of continuous and uniform barrier and copper seed layers on the internal surfaces of the extremely deep vias is very difficult, if not impossible, especially for via depths of 50 μm or more.
FIGS. 1A, 1B, 2A and 2B show exemplary vias of a 3-D integration structure. In FIG. 1A, a barrier layer (not shown) and a seed layer 11 are deposited on an internal surface of a via 1 and field regions 2. Then, copper is electroplated onto surfaces of the seed layer 11 in the via 1 and the field regions 2, as shown in FIG. 1B. Electroplated copper portion 14 is shown as cross-hatched in FIG. 1B. As shown in FIG. 1A, the seed layer 11 has discontinuities 12 and 13 on its sidewalls because continuous and uniform barrier and copper seed layers on the internal surfaces of the extremely deep via 1 is very difficult. The discontinuities 12 and 13 of the seed layer 11 yield voids 15 during electroplating, as shown in FIG. 1B, since electroplating of copper requires good quality copper seed layers on which copper can grow. The void 15 would deteriorate the electrical properties as well as the reliability of the 3-D via.
To avoid the void 15, the seed layer thickness may be increased to make it more continuous within the via. Then, a situation shown in FIG. 2A arises, where excess thickness at the top surface causes narrowing of the via entrance due to copper overhang 16. With reference to FIG. 2B, upon plating copper on and into the structure of FIG. 2A, a center void 17 occurs due to premature closing of the via entrance during plating. The center void 17 of FIG. 2B which may be filled with the plating electrolyte deteriorates the reliability and electrical properties of a resulting 3-D structures, just as the void 15 of FIG. 1B does. Other problems associated with the use of electroplating techniques for 3-D integration include low throughput, since the features to be filled are extremely large and the plating current densities are limited to a range that does not cause voiding in the vias. Such current density range is typically about 2-20 mA/cm2.
Therefore, there is a need for development of new approaches that fills the large features, such as those of 3-D integration structures, with a conductive material such as copper in a cost effective manner without voids and other defects within the features.